1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a charge holding capacitor and a transistor.
2. Related Background Art
Semiconductor memory devices have recently shown a remarkable progress in the memory capacity, principally owing to a fine manufacturing technology.
For example, in a semiconductor memory device having charge holding capacitors and MOS transistors functioning as selector switches, the higher integration has been achieved by compactization of said capacitors and said MOS transistors. However, such charge holding capacitor has a lower limit in the capacity thereof, because a soft error by alpha ray becomes a serious problem. Also the size reduction of the MOS transistors is not easy because of miniaturization technology, performance etc. and has been an obstacle in achieving a higher degree of integration.
In such semiconductor memory device, for reducing the size of the capacitor without reducing the capacity thereof, there has been developed, for example, a method of forming a trench on a silicon substrate and forming the capacitor utilizing the walls of said trench. However in such conventional methods in which the capacitor and the MOS transistor are positioned in a planar structure, the memory cell size is inevitably equal to the sum of the areas of said capacitor and of said MOS transistor, and the degree of integration has therefore approaching to its upper limit.